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Rev.1.02 Jul 01, 2005 page 89 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 12. Timers
Under development
This document is under development and its contents are subject to change.
Figure 12.2 Timer B Configuration
f1 or f2 f8 f32 fC32
1
0
00
01
10
11
TCK1
TMOD1 to TMOD0
00:
Timer mode
10:
Pulse width / period measuring mode
01:
Event counter mode
TCK1 to TCK0
1
0
00
01
10
11
TCK1
TMOD1 to TMOD0
00:
Timer mode
10:
Pulse width / period measuring mode
01:
Event counter mode
TCK1 to TCK0
1
0
00
01
10
11
TCK1
TMOD1 to TMOD0
00:
Timer mode
10:
Pulse width / period measuring mode
01:
Event counter mode
TCK1 to TCK0
1
0
00
01
10
11
TCK1
TMOD1 to TMOD0
00:
Timer mode
10:
Pulse width / period measuring mode
01:
Event counter mode
TCK1 to TCK0
1
0
00
01
10
11
TCK1
TTMOD1 to TMOD0
00:
Timer mode
10:
Pulse width / period measuring mode
01:
Event counter mode
TCK1 to TCK0
1
0
00
01
10
11
TCK1
TMOD1 to TMOD0
00:
Timer mode
10:
Pulse width / period measuring mode
01:
Event counter mode
TCK1 to TCK0
TB0IN
TB1IN
TB2IN
TB3IN
TB4IN
TB5IN
Noise
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Noise
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Noise
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Noise
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Noise
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Noise
filter
Timer B2 overflow or underflow (to a count source of theTimer A)
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Timer B2 interrupt
Timer B3 interrupt
Timer B4 interrupt
Timer B5 interrupt
Timer B0 interrupt
Timer B1 interrupt
PCLK0: Bit in PCLKR register
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register (i = 0 to 5)
NOTE:
1. Be aware that TB5IN shares the pin with RXD2, SCL2 and TA0IN.
1/32
fC32
XCIN
Reset
Clock prescaler
Set the CPSR bit in the
CPSRF register to "1"
(prescaler reset)
1/8
1/4
f1 or f2
f8
f32
1/2
f1
f2
PCLK0 = 0
PCLK0 = 1
Main clock
PLL clock
On-chip
oscillator clock