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Rev.1.02 Jul 01, 2005 page 158 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
14.1.3.7 ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the
ACKC bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the UiSMR4
register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge
of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the
rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
14.1.3.8 Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O operates
as described below.
• The transmit shift register is initialized, and the content of the UiTB register is transferred to the trans-
mit shift register. In this way, the serial I/O starts sending data synchronously with the next clock pulse
applied. However, the UARTi output value does not change state and remains the same as when a
start condition was detected until the first bit of data is output synchronously with the input clock.
• The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
• The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI bit does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.