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Rev.1.02 Jul 01, 2005 page 98 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 12. Timers
Under development
This document is under development and its contents are subject to change.
Figure 12.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
Timer Ai Mode Register (i = 2 to 4)
(When using two-phase pulse signal processing)
Symbol
TA2MR to TA4MR
b6 b5 b4 b3 b2 b1 b0
Operation Mode Select Bit
0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
TCK1
TCK0
010
Bit NameBit Symbol Function
RW
Count Operation Type
Select Bit
Two-Phase Pulse Signal
Processing Operation
Select Bit
(1) (2)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
001
RW
RW
RW
RW
RW
RW
RW
RW
.
To use two-phase pulse signal processing, set this bit to "0".
To use two-phase pulse signal processing, set this bit to "1"
To use two-phase pulse signal processing, set this bit to "0".
NOTES:
1. The TCK1 bit is valid for the TA3MR register. No matter how this bit is set, timers A2 and A4 always operate in normal
processing mode and x4 processing mode, respectively.
2. If two-phase pulse signal processing is desired, following register settings are required:
Set the TAiP bit in the UDF register to "1" (two-phase pulse signal processing function enabled).
Set the TAiTGH and TAiTGL bits in the TRGSR register to "00b" (TAiIN pin input).
Set the port direction bits for TAiIN and TAiOUT to "0" (input mode).
Address After Reset
0398h to 039Ah 00h