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Rev.1.02 Jul 01, 2005 page 81 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 11. DMAC
Under development
This document is under development and its contents are subject to change.
Figure 11.3 DM1SL Register, DM0CON and DM1CON Registers
DMA1 Request Cause Select Register
Symbol Address After Reset
DM1SL 03BAh 00h
DSEL0
DSEL1
DSEL2
DSEL3
DSR
DMS
-
(b5-b4)
FunctionBit Symbol
Bit Name
DMA Request Cause
Select Bit
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
Software DMA
Request Bit
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001b" (software trigger).
The value of this bit when read is "0".
DMA Request Cause
Expansion Select Bit
0 : Basic cause of request
1 : Extended cause of request
See NOTE 1
RW
RW
RW
RW
-
RW
RW
RW
NOTE:
1. The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
DSEL3 to DSEL0 Bits
DMS = 0 (basic cause of request) DMS = 1 (extended cause of request)
Falling edge of INT1 pin
—
Software trigger —
Timer A0 —
Timer A1 —
Timer A2 —
Timer A3
SI/O3
Timer A4
Timer B0
Two edges of INT1 pin
Timer B1
Timer B2
UART0 transmit
—
—
—
SI/O4
UART0 receive/ACK0 —
UART2 transmit —
UART2 receive/ACK2 —
A/D conversion —
UART1 transmit/ACK1 —
b7 b6 b5 b4 b3 b2 b1 b0
DMAi Control Register (i = 0, 1)
DMBIT
DMASL
DMAS
DAD
DSD
-
(b7-b6)
FunctionBit Symbol
Bit Name
Transfer Unit Bit
Select Bit
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
Destination Address
Direction Select Bit
(2)
Source Address Direction
Select Bit
(2)
0 : 16 bits
1 : 8 bits
RW
RW
RW
(1)
RW
-
RW
RW
RW
NOTES:
1. The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
b7 b6 b5 b4 b3 b2 b1 b0
Repeat Transfer Mode
Select Bit
0 : Single transfer
1 : Repeat transfer
DMA Request Bit
DMAE
DMA Enable Bit
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
Symbol Address After Reset
DM0CON 002Ch 00000X00b
DM1CON 003Ch 00000X00b
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b