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Rev.1.02 Jul 01, 2005 page 283 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution
Under development
This document is under development and its contents are subject to change.
22.7 Interrupt
22.7.1 Reading Address 00000h
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to “0”.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among
the enabled interrupts is set to “0”. This causes a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
22.7.2 Setting SP
Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to “0000h”
after reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the
program may go out of control.
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Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
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and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
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22.7.3 NMI Interrupt
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The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
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The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the
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P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
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Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
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NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
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Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
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The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +
300 ns or more.