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Rev.1.02 Jul 01, 2005 page 142 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
Item Specification
Transfer Data Format • Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer Clock • CKDIR bit in UiMR register = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
• The CKDIR bit = 1 (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin. n :Setting value of the UiBRG register 00h to FFh
Transmission, Reception Control
_______ _______ _______ _______
Selectable from CTS function, RTS function or CTS/RTS function disabled
Transmission Start Condition Before transmission can start, the following requirements must be met
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
•
_______ ________
If CTS function is selected, input on the CTSi pin = L
Reception Start Condition Before reception can start, the following requirements must be met
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
Interrupt Request For transmission, one of the following conditions can be selected
Generation Timing • The UiIRS bit
(1)
= 0 (transmit buffer empty): when transferring data from the UiTB register
to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register
(at completion of reception)
Error Detection • Overrun error
(2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
(3)
This error occurs when the number of stop bits set is not detected
• Parity error
(3)
This error occurs when if parity is enabled, the number of 1’s in parity and character
bits does not match the number of 1’s set
• Error sum flag
This flag is set to “1” when any of the overrun, framing, or parity errors occur
Select Function • LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input.
The logic levels of all I/O data is reversed.
•
_______ _______
Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
14.1.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 14.5 lists the specifications of the UART mode. Table 14.6 lists the registers used in
UART mode and the register values set.
Table 14.5 UART Mode Specifications
i = 0 to 2
NOTES:
1. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.
2. If an overrun error occurs, the value of the UiRB register will be indeterminate. The IR bit in the SiRIC register does not change.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the
UARTi receive register to the UiRB register.