Filter
Top Products
Rev.1.02 Jul 01, 2005 page 210 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module
Under development
This document is under development and its contents are subject to change.
18.5 Operational Modes
The CAN module has the following four operational modes.
• CAN Reset/Initialization Mode
• CAN Operation Mode
• CAN Sleep Mode
• CAN Interface Sleep Mode
Figure 18.13 shows transition between operational modes.
Figure 18.13 Transition Between Operational Modes
18.5.1 CAN Reset/Initialization Mode
The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit in the C0CTLR
register to “1”. If the Reset bit is set to “1”, check that the State_Reset bit in the C0STR register is set to “1”.
Entering the CAN reset/initialization mode initiates the following functions by the module:
• CAN communication is impossible.
• When the CAN reset/initialization mode is activated during an ongoing transmission in operation
mode, the module suspends the mode transition until completion of the transmission (successful,
arbitration loss, or error detection). Then, the State_Reset bit is set to “1”, and the CAN reset/initialization
mode is activated.
• The C0MCTLj (j = 0 to 15), C0STR, C0ICR, C0IDR, C0RECR, C0TECR and C0TSR registers are
initialized. All these registers are locked to prevent CPU modification.
• The C0CTLR, C0CONR, C0GMR, C0LMAR and C0LMBR registers and the CAN0 message box retain
their contents and are available for CPU access.
MCU Reset
CAN reset/initialization
mode
State_Reset = 1
CAN operation mode
State_Reset = 0
CAN sleep mode
CAN interface
sleep mode
Bus off state
State_BusOff = 1
Reset = 0
CCLK3 = 1
Sleep = 1
and
Reset = 0
Sleep = 0
and
Reset = 1
TEC > 255
when 11 consecutive
recessive bits are
detected 128 times
or
RetBusOff = 1
CCLK3 = 0
Reset = 1
Reset = 1
CCLK3: Bit in CCLKR register
Reset, Sleep, RetBusOff: Bits in C0CTLR register
State_Reset, State_BusOff: Bits in C0STR register