Filter
Top Products
Rev.1.02 Jul 01, 2005 page 221 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module
Under development
This document is under development and its contents are subject to change.
18.15.2 Transmission
Figure 18.22 shows the timing of the transmit sequence.
CTX
TrmReq bit
TrmActive bit
CAN0 Successful
Transmission Interrupt
TrmState bit
TrmSucc bit
MBOX bit
SentData bit
SOF SOF
Transmission slot No.
C0MCTLj register
C0STR register
(1)
(2)
(2)
(1)
(1)
(3)
(4)
(3)
(3)
j = 0 to 15
EOF IFSACK
Figure 18.22 Timing of Transmit Sequence
(1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to “1” (Transmission slot) in the bus idle
state, the TrmActive bit in the C0MCTLj register and the TrmState bit in the C0STR register are set to
“1” (Transmitting/Transmitter), and CAN module starts the transmission.
(2) If the arbitration is lost after the CAN module starts the transmission, the TrmActive and TrmState bits
are set to “0”.
(3) If the transmission has been successful without lost in arbitration, the SentData bit in the C0MCTLj
register is set to “1” (Transmission is successfully completed) and TrmActive bit is set to “0” (Waiting
for bus idle or completion of arbitration). And when the interrupt enable bits in the C0ICR register = 1
(Interrupt enabled), CAN0 successful transmission interrupt request is generated and the MBOX (the
slot number which transmitted the message) and TrmSucc bit in the C0STR register are changed.
(4) When starting the next transmission, set the SentData and TrmReq bits to “0”. And set the TrmReq bit
to “1” after checking that the SentData and TrmReq bits are set to “0”.