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Rev.1.02 Jul 01, 2005 page 127 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 14.4 UARTi Transmit/Receive Unit
SP SP
PAR
2SP
1SP
UART
TXDi
D8 D7 D6 D5 D4 D3 D2 D1 D0
2SP
1SP
UART
RXDi
D7 D6 D5 D4 D3 D2 D1 D0D80000000
SP SP
PAR
SMD2 to SMD0
0
1
IOPOL
STPS
IOPOL
UiERE
PRYE
0
1
1
0
1
0
1
0
1
0
1
0
SMD2 to SMD0
0
1
0
1
0
1
0
1
0
1
0
1
STPS
PRYE
Reverse
No reverse
RXD data
reverse circuit
Clock
synchronous
type
PAR
enabled
PAR
disabled
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
UART(7 bits)
UART
(9 bits)
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
UARTi receive register
UiTB register
UiRB register
Data bus low-order bits
Data bus high-order bits
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
UART(7 bits)
UARTi transmit register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
Clock
synchronous type
PAR
disabled
PAR
enabled
Error signal
output circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
TXD data
reverse circuit
i = 0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register
UiERE: Bit in UiC1 register
UART
(9 bits)