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Rev.1.02 Jul 01, 2005 page 146 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
• Example of Receive Timing when Transfer Data is 8-bit Long (parity disabled, one stop bit)
The above timing diagram applies to the case where the register bits are set as follows:
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
i = 0 to 2
"1"
"0"
"0"
"1"
"H"
"L"
"0"
"1"
UiBRG count
source
RXDi
Transfer clock
RTSi
RE bit in
UiC1 register
RI bit in
UiC1 register
IR bit in
SiRIC register
D0
Start bit
Sampled "L"
Stop bit
Reception triggered when transfer clock
is generated by falling edge of start bit
Set to "0" by an interrupt request acknowledgement or by program
Receive data taken in
D7
D1
Transferred from UARTi receive
register to UiRB register
Figure 14.18 Receive Operation
14.1.2.1 Bit Rates
In UART mode, the frequency set by the UiBRG register (i = 0 to 2) divided by 16 become the bit rates.
Table 14.9 lists example of bit rates and settings.
Table 14.9 Example of Bit Rates and Settings
Bit-rate Count source
Peripheral function clock: 16MHz Peripheral function clock: 24MHz
(bps) of BRG
Set value of BRG: n Actual time (bps) Set value of BRG: n Actual time (bps)
1200 f8 103 (67h) 1202 155 (9Bh) 1202
2400 f8 51 (33h) 2404 77 (4Dh) 2404
4800 f8 25 (19h) 4808 38 (26h) 4808
9600 f1 103 (67h) 9615 155 (9Bh) 9615
14400 f1 68 (44h) 14493 103 (67h) 14423
19200 f1 51 (33h) 19231 77 (4Dh) 19231
28800 f1 34 (22h) 28571 51 (33h) 28846
31250 f1 31 (1Fh) 31250 47 (2Fh) 31250
38400 f1 25 (19h) 38462 38 (26h) 38462
51200 f1 19 (13h) 50000 28 (1Ch) 51724