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Rev.1.02 Jul 01, 2005 page 152 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
Table 14.11 Registers to Be Used and Settings in I
2
C Mode
Register Bit
Function
Master Slave
UiTB
(1)
0 to 7 Set transmission data
UiRB
(1)
0 to 7 Reception data can be read
8 ACK or NACK is set in this bit
ABT Arbitration lost detection flag Invalid
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate Invalid
UiMR
(1)
SMD2 to SMD0 Set to “010b”
CKDIR Set to “0” Set to “1”
IOPOL Set to “0”
UiC0 CLK1, CLK0
Select the count source for the UiBRG register
Invalid
CRS Invalid because the CRD bit = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Set to “1”
CKPOL Set to “0”
UFORM Set to “1”
UiC1 TE
Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS
(2)
Invalid
U2RRM
(2)
, Set to “0”
UiLCH, UiERE
UiSMR IICM Set to “1”
ABC Select the timing at which arbitration-lost Invalid
is detected
BBS Bus busy flag
3 to 7 Set to “0”
UiSMR2 IICM2 See Table 14.12 I
2
C Mode Functions
CSC
Set this bit to “1” to enable clock synchronization
Set to “0”
SWC
Set this bit to “1” to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock
ALS Set this bit to “1” to have SDAi output Set to “0”
stopped when arbitration-lost is detected
STAC Set to “0” Set this bit to “1” to initialize UARTi at
start condition detection
SWC2 Set this bit to “1” to have SCLi output forcibly pulled low
SDHI Set this bit to “1” to disable SDAi output
7 Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0”
CKPH See Table 14.12 I
2
C Mode Functions
DL2 to DL0 Set the amount of SDAi digital delay
UiSMR4 STAREQ
Set this bit to “1” to generate start condition
Set to “0”
RSTAREQ
Set this bit to “1” to generate restart condition
Set to “0”
STPREQ
Set this bit to “1” to generate stop condition
Set to “0”
STSPSEL
Set this bit to “1” to output each condition
Set to “0”
ACKD Select ACK or NACK
ACKC Set this bit to “1” to output ACK data
SCLHI Set this bit to “1” to have SCLi output Set to “0”
stopped when stop condition is detected
SWC9 Set to “0”
Set this bit to “1” to set the SCLi to “L” hold
at the falling edge of the 9th bit of clock
IFSR0 IFSR06, ISFR07 Set to “1”
UCON U0IRS, U1IRS Invalid
2 to 7 Set to “0”
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in I
2
C mode.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON
register.