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4.59ControlStatusRegisterforPeripheralTransmitEndpoint(PERI_TXCSR)
Registers
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TheControlStatusRegisterforPeripheralTransmitEndpoint(PERI_TXCSR)isshowninFigure74and
describedinTable75.
Figure74.ControlStatusRegisterforPeripheralTransmitEndpoint(PERI_TXCSR)
15141312111097
ReservedISOMODEDMAENFRCDATATOGDMAMODEReserved
R-0R/W-0R/W-0R/W-0R/W-0R/W-0R-0
6543210
CLRDATATOGSENTSTALLSENDSTALLFLUSHFIFOUNDERRUNFIFONOTEMPTYTXPKTRDY
W-0R/W-0R/W-0W-0R/W-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;W=Writeonly;-n=valueafterreset
Table75.ControlStatusRegisterforPeripheralTransmitEndpoint(PERI_TXCSR)
FieldDescriptions
BitFieldValueDescription
15Reserved0Reserved
14ISO0-1SetthisbittoenabletheTxendpointforIsochronoustransfers,andclearthisbittoenabletheTx
endpointforBulkorInterrupttransfers.
13MODE0-1SetthisbittoenabletheendpointdirectionasTx,andclearthisbittoenableitasRx.
Note:ThisbithasanyeffectonlywherethesameendpointFIFOisusedforbothTransmitand
Receivetransactions.
12DMAEN0-1SetthisbittoenabletheDMArequestfortheTxendpoint.
11FRCDATATOG0-1Setthisbittoforcetheendpointdatatoggletoswitchandthedatapackettobeclearedfromthe
FIFO,regardlessofwhetheranACKwasreceived.ThiscanbeusedbyInterruptTxendpoints
thatareusedtocommunicateratefeedbackforIsochronousendpoints.
10DMAMODE0-1WhenusingDMA,clearthisbittoreceiveaninterruptforeachpacket,orsetthisbittoonly
receiveerrorinterrupts.
9-7Reserved0Reserved
6CLRDATATOG0-1Setthisbittoresettheendpointdatatoggleto0.
5SENTSTALL0-1ThisbitissetautomaticallywhenaSTALLhandshakeistransmitted.TheFIFOisflushedandthe
TXPKTRDYbitiscleared.Youshouldclearthisbit.
4SENDSTALL0-1SetthisbittoissueaSTALLhandshaketoanINtoken.Clearthisbittoterminatethestall
condition.
Note:ThisbithasnoeffectwheretheendpointisbeingusedforIsochronoustransfers.
3FLUSHFIFO0-1SetthisbittoflushthenextpackettobetransmittedfromtheendpointTxFIFO.TheFIFOpointer
isresetandtheTXPKTRDYbitiscleared.
Note:FlushFIFOhasnoeffectunlessTXPKTRDYisset.Alsonotethat,iftheFIFOis
double-buffered,FlushFIFOmayneedtobesettwicetocompletelycleartheFIFO.
2UNDERRUN0-1ThisbitissetautomaticallyifanINtokenisreceivedwhenTXPKTRDYisnotset.Youshould
clearthisbit.
1FIFONOTEMPTY0-1Thisbitissetwhenthereisatleast1packetintheTxFIFO.Youshouldclearthisbit.
0TXPKTRDY0-1SetthisbitafterloadingadatapacketintotheFIFO.Itisclearedautomaticallywhenadatapacket
hasbeentransmitted.Aninterruptisgenerated(ifenabled)whenthebitiscleared.
UniversalSerialBus(USB)Controller 122SPRUGH3–November2008
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