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3.3.2.4ReceiveQueue
SOP descriptor Buffer
Descriptor Buffer
Descriptor
Descriptor
Buffer
Buffer
EOP descriptor Buffer
Rx queue head descriptor pointer
3.3.2.5Operation
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USBControllerHostandPeripheralModesOperation
Figure15showsanRxQueue.RxqueueprovidealogicalqueueofprocessormemoryspaceforDMA
packetstobereceivedfromDMAcontrollerchannel.EachchannelhassingleRxqueue.Thereareno
multiplequeueasintransmitchannels.EachqueuehasoneassociatedRxQueueHeadDescriptor
PointerandoneassociatedRxCompletionPointercontainedinthechannelRxDMAState.TheRxqueue
arelinkedlistsofRxbufferdescriptorsthatconstituteprocessormemoryspaceforoneormorepacketsto
bereceived.Packetspaceisaddedtothetailofthelistbythesoftwareandreceivedpacketsarefreed
fromthelistbytheDMAcontrolleraseachpacketisreceived.
Figure15.RxQueueFlowChart
•AfterresetthesoftwaremustwritezeroestoallRxDMAStateregisters(RCPPIDMASTATEW0,
RCPPIDMASTATEW1,RCPPIDMASTATEW2,RCPPIDMASTATEW3,RCPPIDMASTATEW4,
RCPPIDMASTATEW5andRCPPIDMASTATEW6).
•Thesoftwareconstructsreceivequeueinmemory.
•EnableDMAfortheendpointinthePERI_RXCSRorHOST_RXCSRbysettingtheDMAENbit.
•EnabletheDMAportsbysettingRCPPI_ENABLEbitofRCPPICRregister.
•SetthevalueinRBUFCNTnregister(wherenisthechannelnumber)forthenumberofbuffers
availableintheRxqueue.Thehardwarerequiresatleast3availablebufferstostarttheDMA.Anew
transferwillnotbestartedifthebuffercountisbelow3.ThevalueinRBUFCNTndecrementsasDMA
controllerconsumesthebuffersforreception.
•WritetheheadofthequeuedescriptorpointertotheRCPPIDMASTATEW1registertostarttheDMA.
•TheUSBcontrollerwillsendINtokenandwaitforthedataonthebus.Oncedataisreceived,DMA
controllerwilltransferthedataintheRxqueuefromtheendpointFIFO.OnceacompleteDMApacket
isreceived,interruptassociatedwiththeDMAchannelisasserted.
SPRUGH3–November2008UniversalSerialBus(USB)Controller65
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