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TX mode
Write
MaxP bytes
to FIFO
Last
packet
?
No
Yes
Set TxPktRdy
and set DataEnd
state −> IDLE
Return
TxPktRdy
Set
USBControllerHostandPeripheralModesOperation
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3.1.1.5.2TXMode
WhentheendpointisinTXstateallarrivingINtokensneedtobetreatedaspartofadataphaseuntilthe
requiredamountofdatahasbeensenttothehost.IfeitheraSETUPoranOUTtokenisreceivedwhile
theendpointisintheTXstate,thiswillcauseaSetupEndconditiontooccurasthecoreexpectsonlyIN
tokens.SeeFigure7.
ThreeeventscancauseTXmodetobeterminatedbeforetheexpectedamountofdatahasbeensent:
1.ThehostsendsaninvalidtokencausingaSETUPENDcondition(bit4ofPERI_CSR0set).
2.Thesoftwaresendsapacketcontaininglessthanthemaximumpacketsizeforendpoint0.
3.Thesoftwaresendsanemptydatapacket.
Untilthetransactionisterminated,thesoftwaresimplyneedstoloadtheFIFOwhenitreceivesan
interruptthatindicatesapackethasbeensentfromtheFIFO.(Aninterruptisgeneratedwhen
TXPKTRDYiscleared.)
Whenthesoftwareforcestheterminationofatransfer(bysendingashortoremptydatapacket),itshould
settheDATAENDbitofPERI_CSR0(bit3)toindicatetothecorethatthedataphaseiscompleteand
thatthecoreshouldnextreceiveanacknowledgepacket.
Figure7.TXModeFlowChart
34UniversalSerialBus(USB)ControllerSPRUGH3–November2008
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