Filter
Top Products
4.19TransmitCPPIInterruptEnableSetRegister(TCPPIIENSETR)
4.20TransmitCPPIInterruptEnableClearRegister(TCPPIIENCLRR)
Registers
www.ti.com
TheTransmitCPPIInterruptEnableSetRegister(TCPPIIENSETR)isshowninFigure34anddescribed
inTable35.
Figure34.TransmitCPPIInterruptEnableSetRegister(TCPPIIENSETR)
3116
Reserved
R-0
15430
ReservedCOMP_PENDING_INTR_EN
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table35.TransmitCPPIInterruptEnableSetRegister(TCPPIIENSETR)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3-0COMP_PENDING_INTR_EN0-FhTransmitCPPIHighPriorityInterruptEnables
TheseareactivehighinterruptenablescorrespondingtotheTransmitCPPIHigh
PriorityCompletionPendingstatusbits.
TheTransmitCPPIInterruptEnableClearRegister(TCPPIIENCLRR)isshowninFigure35and
describedinTable36.
Figure35.TransmitCPPIInterruptEnableClearRegister(TCPPIIENCLRR)
3116
Reserved
R-0
15430
ReservedCOMP_PENDING_INTR_EN
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table36.TransmitCPPIInterruptEnableClearRegister(TCPPIIENCLRR)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3-0COMP_PENDING_INTR_EN0-FhWritinga1toanyofthebitsintheTransmitCPPIInterruptEnableClearRegisterwill
resultinclearingofthecorrespondingbitintheTransmitCPPIHighPriorityInterrupt
EnableRegister.
UniversalSerialBus(USB)Controller 96SPRUGH3–November2008
SubmitDocumentationFeedback