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4.21ReceiveCPPIControlRegister(RCPPICR)
4.22ReceiveCPPIMaskedStatusRegister(RCPPIMSKSR)
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Registers
TheReceiveCPPIControlRegister(RCPPICR)isshowninFigure36anddescribedinTable37.
Figure36.ReceiveCPPIControlRegister(RCPPICR)
3116
Reserved
R-0
1510
ReservedRCPPI_ENABLE
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table37.ReceiveCPPIControlRegister(RCPPICR)FieldDescriptions
BitFieldValueDescription
31-1Reserved0Reserved
0RCPPI_ENABLEReceiveCPPIEnableControlsiftheReceiveCPPIDMAcontrollerisenabled.Besuretoprogram
theCPPIchainandsettheDMAstatewordsbeforeenablingtheDMA.FailuretoinitializetheDMA
beforeenablingcouldresultinspurioustransfersandmemorycorruption.
0ReceiveCPPIDMAisdisabled.
1ReceiveCPPIDMAisenabled.
TheReceiveCPPIMaskedStatusRegister(RCPPIMSKSR)isshowninFigure37anddescribedin
Table38.
Figure37.ReceiveCPPIMaskedStatusRegister(RCPPIMSKSR)
3116
Reserved
R-0
15430
ReservedMASKED_COMP_PENDING
R-0R-0
LEGEND:R=Readonly;-n=valueafterreset
Table38.ReceiveCPPIMaskedStatusRegister(RCPPIMSKSR)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3-0MASKED_COMP_PENDING0-FhMaskedReceiveCompletionPending
Indicatorsforchannels3to0RawReceivecompletionindicatorsbitwiseANDedwith
Receivecompletionmaskbits
SPRUGH3–November2008UniversalSerialBus(USB)Controller97
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