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IntSetup
IN data
phase
Int
IN data
phase
Int
IN data
phase
Int
Status phase
(OUT)
IntSequence #1
Idle TX state Idle
set TxPktRdy
Load FIFO and
and set DataEnd
Load FIFO
and set
TxPktRdy
Unload device
req. and clear
RxPktRdy
Load FIFO
and set
TxPktRdy
CPU actions
Status phase
Setup
CPU actions
Sequence #2
RxPktRdy
and clear
Unload FIFO
OUT data
Idle
Unload FIFO
and clear
RxPktRdy
phase
OUT data
Int Int
phase
clear RxPktRdy
Unload FIFO and
and set DataEnd
Int
OUT data
phase
Int
(IN)
Int
RX state Idle
Unload
device req.
and clear
RxPktRdy
Setup IntSequence #3
Status phase
(IN)
Int
No data phase
DataEnd
clear RxPktRdy and set
Unload device req and
Idle
CPU actions
USBControllerHostandPeripheralModesOperation
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Figure4.SequenceofTransfer
30UniversalSerialBus(USB)ControllerSPRUGH3–November2008
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