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3.2.3HostMode:InterruptTransactions
USBControllerHostandPeripheralModesOperation
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•TheHOST_TXINTERVALregisterneedstobewrittenwiththerequiredvaluefortheNAKlimit(2-215
frames/microframes),orclearedto0iftheNAKtimeoutfeatureisnotrequired.
•TherelevantinterruptenablebitintheINTRTXEregistershouldbeset(ifaninterruptisrequiredfor
thisendpoint).
•ThefollowingbitsofHOST_TXCSRregistershouldbesetasshownbelow:
–SettheMODEbit(bit13)to1toensuretheFIFOisenabled(onlynecessaryiftheFIFOisshared
withanRxendpoint).
–SettheDMAENbit(bit12)to1ifaDMArequestisrequiredforthisendpoint.
–CleartheFRCDATATOGbit(bit11)to0toallownormaldatatoggleoperations.
–SettheDMAMODEbit(bit10)to1whenDMAisenabledandtheendpointinterruptisnotneeded
foreachpackettransmission.
Whentheendpointisfirstconfigured,theendpointdatatoggleshouldbeclearedto0eitherbyusingthe
DATATOGWRENbitandDATATOGbitofHOST_TXCSR(bit9andbit8)totogglethecurrentsettingor
bysettingtheCLRDATATOGbitofHOST_TXCSR(bit6).Thiswillensurethatthedatatoggle(whichis
handledautomaticallybythecontroller)startsinthecorrectstate.Also,ifthereareanydatapacketsin
theFIFO(indicatedbytheFIFONOTEMPTYbitofHOST_TXCSRregister(bit1)beingset),theyshould
beflushedbysettingtheFLUSHFIFObit(bit3ofHOST_TXCSR).
Note:Itmaybenecessarytosetthisbittwiceinsuccessionifdoublebufferingisenabled.
3.2.2.2.2Operation
WhenBulkdataisrequiredtobesenttotheUSBperipheraldevice,thesoftwareshouldwritethefirst
packetofthedatatotheFIFO(ortwopacketsifdouble-buffered)andsettheTXPKTRDYbitinthe
correspondingHOST_TXCSRregister(bit0).ThecontrollerwillthensendanOUTtokentotheselected
peripheralendpoint,followedbythefirstdatapacketfromtheFIFO.
Ifdataiscorrectlyreceivedbytheperipheraldevice,anACKshouldbereceivedwhereuponthecontroller
willclearTXPKTRDYbitofHOST_TXCSR(bit0).IftheUSBperipheraldevicerespondswithaSTALL,
theRXSTALLbit(bit5)ofHOST_TXCSRisset.IfaNAKisreceived,thecontrollertriesagainand
continuestotryuntileitherthetransactionissuccessfulortheNAKlimitsetintheHOST_TXINTERVAL
registerisreached.Ifnoresponseatallisreceived,twofurtherattemptsaremadebeforethecontroller
reportsanerrorbysettingERRORbitinHOST_TXCSR(bit2).
Thecontrollerthengeneratestheappropriateendpointinterrupt,whereuponthesoftwareshouldreadthe
correspondingHOST_TXCSRregistertodeterminewhethertheRXSTALL(bit5),ERROR(bit2)or
NAK_TIMEOUT(bit7)bitissetandactaccordingly.IftheNAK_TIMEOUTbitisset,thecontrollercanbe
directedeithertocontinuetryingthistransaction(untilittimesoutagain)byclearingtheNAK_TIMEOUT
bitortoabortthetransactionbyflushingtheFIFObeforeclearingtheNAK_TIMEOUTbit.
Iflargeblocksofdataarebeingtransferred,thentheoverheadofcallinganinterruptserviceroutineto
loadeachpacketcanbeavoidedbyusingDMA.
3.2.2.2.3ErrorHandling
IfthetargetwantstoshutdowntheBulkOUTpipe,itwillsendaSTALLresponse.Thisisindicatedbythe
RXSTALLbitofHOST_TXCSRregister(bit5)beingset.
Whenthecontrollerisoperatingasthehost,interactionswithanInterruptendpointontheUSBperipheral
devicearehandledinverymuchthesamewayastheequivalentBulktransactions(describedinprevious
sections).
TheprincipaldifferenceasfarasoperationalstepsareconcernedisthatPROTfieldofHOST_RXTYPE
andHOST_TXTYPE(bits5:4)needtobeset(binaryvalue)torepresentanInterrupttransaction.
TherequiredpollingintervalalsoneedstobesetintheHOST_RXINTERVALandHOST_TXINTERVAL
registers.
UniversalSerialBus(USB)Controller 54SPRUGH3–November2008
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