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3.1.1.5Endpoint0ServiceRoutine
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USBControllerHostandPeripheralModesOperation
AnEndpoint0interruptisgeneratedwhen:
•ThecontrollersetstheRXPKTRDYbitofPERI_CSR0(bit0)afteravalidtokenhasbeenreceivedand
datahasbeenwrittentotheFIFO.
•ThecontrollerclearstheTXPKTRDYbitofPERI_CSR0(bit1)afterthepacketofdataintheFIFOhas
beensuccessfullytransmittedtothehost.
•ThecontrollersetstheSENTSTALLbitofPERI_CSR0(bit2)afteracontroltransactionisendeddue
toaprotocolviolation.
•ThecontrollersetstheSETUPENDbitofPERI_CSR0(bit4)becauseacontroltransferhasended
beforeDATAEND(bit3ofPERI_CSR0)isset.
Whenevertheendpoint0serviceroutineisentered,thesoftwaremustfirstchecktoseeifthecurrent
controltransferhasbeenendedduetoeitheraSTALLconditionoraprematureendofcontroltransfer.If
thecontroltransferendsduetoaSTALLcondition,theSENTSTALLbitwouldbeset.Ifthecontrol
transferendsduetoaprematureendofcontroltransfer,theSETUPENDbitwouldbeset.Ineithercase,
thesoftwareshouldabortprocessingthecurrentcontroltransferandsetthestatetoIDLE.
Oncethesoftwarehasdeterminedthattheinterruptwasnotgeneratedbyanillegalbusstate,thenext
actiontakendependsontheendpointstate.Figure5showstheflowofthisprocess.
Ifendpoint0isinIDLEstate,theonlyvalidreasonaninterruptcanbegeneratedisasaresultofthe
controllerreceivingdatafromthebus.TheserviceroutinemustcheckforthisbytestingtheRXPKTRDY
bitofPERI_CSR0(bit0).Ifthisbitisset,thenthecontrollerhasreceivedaSETUPpacket.Thismustbe
unloadedfromtheFIFOanddecodedtodeterminetheactionthecontrollermusttake.Dependingonthe
commandcontainedwithintheSETUPpacket,endpoint0willenteroneofthreestates:
•Ifthecommandisasinglepackettransaction(SET_ADDRESS,SET_INTERFACEetc.)withoutany
dataphase,theendpointwillremaininIDLEstate.
•IfthecommandhasanOUTdataphase(SET_DESCRIPTORetc.),theendpointwillenterRXstate.
•IfthecommandhasanINdataphase(GET_DESCRIPTORetc.),theendpointwillenterTXstate.
Iftheendpoint0isinTXstate,theinterruptindicatesthatthecorehasreceivedanINtokenanddata
fromtheFIFOhasbeensent.ThesoftwaremustrespondtothiseitherbyplacingmoredataintheFIFOif
thehostisstillexpectingmoredataorbysettingtheDATAENDbittoindicatethatthedataphaseis
complete.Oncethedataphaseofthetransactionhasbeencompleted,endpoint0shouldbereturnedto
IDLEstatetoawaitthenextcontroltransaction.
Note:Allcommandtransactionsincludeafieldthatindicatestheamountofdatathehostexpects
toreceiveorisgoingtosend.
IftheendpointisinRXstate,theinterruptindicatesthatadatapackethasbeenreceived.Thesoftware
mustrespondbyunloadingthereceiveddatafromtheFIFO.Thesoftwaremustthendeterminewhetherit
hasreceivedalloftheexpecteddata.Ifithas,thesoftwareshouldsettheDATAENDbitandreturn
endpoint0toIDLEstate.Ifmoredataisexpected,thefirmwareshouldsettheSERV_RXPKTRDYbitof
PERI_CSR0(bit6)toindicatethatithasreadthedataintheFIFOandleavetheendpointinRXstate.
SPRUGH3–November2008UniversalSerialBus(USB)Controller31
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