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4.23ReceiveCPPIRawStatusRegister(RCPPIRAWSR)
4.24ReceiveCPPIInterruptEnableSetRegister(RCPPIENSETR)
Registers
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TheReceiveCPPIRawStatusRegister(RCPPIRAWSR)isshowninFigure38anddescribedin
Table39.
Figure38.ReceiveCPPIRawStatusRegister(RCPPIRAWSR)
3116
Reserved
R-0
15430
ReservedCOMP_PENDING
R-0R-0
LEGEND:R=Readonly;-n=valueafterreset
Table39.ReceiveCPPIRawStatusRegister(RCPPIRAWSR)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3-0COMP_PENDING0-FhRawReceiveCompletionPending
Indicatorsforchannels3to0Activehighflagswhichindicatethatapackethascompleted
reception
TheReceiveCPPIInterruptEnableSetRegister(RCPPIENSETR)isshowninFigure39anddescribedin
Table40.
Figure39.ReceiveCPPIInterruptEnableSetRegister(RCPPIENSETR)
3116
Reserved
R-0
15430
ReservedCOMP_PENDING_INTR_EN
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table40.ReceiveCPPIInterruptEnableSetRegister(RCPPIENSETR)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3-0COMP_PENDING_INTR_EN0-FhReceiveCPPIInterruptEnables
TheseareactivehighinterruptenablescorrespondingtotheReceiveCPPICompletion
Pendingstatusbits.Writinga1toanyofthebitsintheReceiveCPPIInterruptEnable
SetRegisterwillresultinsettingofthecorrespondingbitintheReceiveCPPIInterrupt
EnableRegister.
98UniversalSerialBus(USB)ControllerSPRUGH3–November2008
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