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4.62ControlStatusRegisterforPeripheralReceiveEndpoint(PERI_RXCSR)
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Registers
TheControlStatusRegisterforPeripheralReceiveEndpoint(PERI_RXCSR)isshowninFigure77and
describedinTable78.
Figure77.ControlStatusRegisterforPeripheralReceiveEndpoint(PERI_RXCSR)
1514131211108
ReservedISODMAENDISNYETDMAMODEReserved
R-0R/W-0R/W-0R/W-0R/W-0R-0
76543210
CLRDATATOGSENTSTALLSENDSTALLFLUSHFIFODATAERROROVERRUNFIFOFULLRXPKTRDY
W-0R/W-0R/W-0W-0R-0R/W-0R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;W=Writeonly;-n=valueafterreset
Table78.ControlStatusRegisterforPeripheralReceiveEndpoint(PERI_RXCSR)
FieldDescriptions
BitFieldValueDescription
15Reserved0Reserved
14ISO0-1SetthisbittoenabletheReceiveendpointforIsochronoustransfers,andclearthisbittoenablethe
ReceiveendpointforBulk/Interrupttransfers.
13DMAEN0-1SetthisbittoenabletheDMArequestfortheReceiveendpoints.
12DISNYET0-1SetthisbittodisablethesendingofNYEThandshakes.Whenset,allsuccessfullyreceived
ReceivepacketsareACKed,includingatthepointatwhichtheFIFObecomesfull.
Note:Thisbitonlyhasanyeffectinhigh-speedmode,inwhichmodeitshouldbesetforall
Interruptendpoints.
11DMAMODE0Thisbitshouldalwaysbeclearedto0.
10-8Reserved0Reserved
7CLRDATATOG0-1Setthisbittoresettheendpointdatatoggleto0.
6SENTSTALL0-1ThisbitissetwhenaSTALLhandshakeistransmitted.TheFIFOisflushedandtheTXPKTRDYbit
iscleared.Youshouldclearthisbit.
5SENDSTALL0-1SetthisbittoissueaSTALLhandshake.Clearthisbittoterminatethestallcondition.
Note:ThisbithasnoeffectwheretheendpointisbeingusedforIsochronoustransfers.
4FLUSHFIFO0-1SetthisbittoflushthenextpackettobereadfromtheendpointReceiveFIFO.TheFIFOpointeris
resetandtheRXPKTRDYbitiscleared.
Note:FLUSHFIFOhasnoeffectunlessRXPKTRDYisset.Alsonotethat,iftheFIFOis
double-buffered,FLUSHFIFOmayneedtobesettwicetocompletelycleartheFIFO.
3DATAERROR0-1ThisbitissetwhenRXPKTRDYissetifthedatapackethasaCRCorbit-stufferror.Itiscleared
whenRXPKTRDYiscleared.
Note:ThisbitisonlyvalidwhentheendpointisoperatinginISOmode.InBulkmode,italways
returnszero.
2OVERRUN0-1ThisbitissetifanOUTpacketcannotbeloadedintotheReceiveFIFO.Youshouldclearthisbit.
Note:ThisbitisonlyvalidwhentheendpointisoperatinginISOmode.InBulkmode,italways
returnszero.
1FIFOFULL0-1ThisbitissetwhennomorepacketscanbeloadedintotheReceiveFIFO.
0RXPKTRDY0-1Thisbitissetwhenadatapackethasbeenreceived.Youshouldclearthisbitwhenthepackethas
beenunloadedfromtheReceiveFIFO.Aninterruptisgeneratedwhenthebitisset.
SPRUGH3–November2008UniversalSerialBus(USB)Controller125
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