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3.4.1USBCoreInterrupts
3.4.2DMAInterrupts
3.5TestModes
USBControllerHostandPeripheralModesOperation
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TherearetwomethodsavailableforsoftwaretoaccessUSBcoreinterrupts,selectablebytheUINTbitof
CTRLR.TheUINTbitclearedto0selectsthePDR2.0compliantregisterset(INTSRCR,INTSETR,
INTCLRR,INTMSKR,INTMSKSETR,INTMSKCLRR,INTMASKEDR).Thisisthedefault,andshouldbe
usedformostsystems.TheDRVVBUSlevelchangeinterruptisonlyavailableinthePDRcompliant
register.UINTsettooneselectsdirectaccesstotheUSBcoreinterruptregisters(INTRUSB,INTRUSBE,
INTRTX,INTRRX).Softwareshouldselectasinglemethodforinterruptsanduseitscorresponding
registersexclusively.
InterruptstatuscanbedeterminedusingtheINTSRCR(interruptsource)register.Thisregisteris
non-masked.Tocleartheinterruptsource,setthecorrespondinginterruptbitinINTCLRRregister.For
debuggingpurposes,interruptcanbesetmanuallythroughINTSETRregister.
Theinterruptcontrollerprovidestheoptionofmaskingtheinterrupts.Amaskcanbesetusing
INTMSKSETRregisterandcanbeclearedbysettingthecorrespondingbitintheINTMSKCLRRregister.
ThemaskcanbereadfromINTMSKRregister.Themaskedinterruptstatusisdeterminedusingthe
INTMASKEDRregister.
SoftwareshouldwriteallzerostotheEndOfInterruptRegister(EOIR)toacknowledgethecompletionof
theUSBcoreinterrupt.
Note:IftheEOIRisnotwritten,theinterruptoutputtotheCPUwillnotbepulsedagainforthenext
interrupt.
InterruptstatusfortheDMAinterruptsisdeterminedbyTCCPIRAWSRandRCPPIRAWSRregisters.
ThesearetherawinterruptstatusregistersforDMAinterrupts.
TxDMAinterruptsmaskissetusingTCPPIENSETRregisterandclearedusingTCPPIIENCLRRregister.
ThemaskedstatusisreadusingTCPPIMSKSRregister.
RxDMAinterruptsmaskissetusingRCPPIENSETRregisterandclearedusingRCPPIIENCLRRregister.
ThemaskedstatusisreadusingRCPPIMSKSRregister.
LikeUSBcoreinterrupts,theCPPIEOIRregisterneedstobewrittenbythehostprocessorsoftwareto
acknowledgethecompletionoftheinterrupt.
UponreceiptofaDMAinterrupt,softwareshouldcheckTCPPIRAWSR/RCPPIRAWSRtodetermine
whichDMAchannel(s)toservice.ChecktheCPPIbufferdescriptorownershipfieldforthecompleted
channelforerrorconditionsandaddorupdatebufferdescriptorsasneeded.WritetheRCPPICOMPPTR
orTCPPICOMPPTRcompletionpointerwiththeaddressofthebufferdescriptorservicedinordertoclear
theinterrupt.Finally,writetheDMAEndOfInterruptregisterCPPIEOIRwithallzerostoenablefuture(or
currentunserviced)interruptstopulsetheinterruptoutputtotheCPU.
WhenusingDMAwithaTXendpoint,settheTXCSRregisterDMAMODEbittooneinordertoreceive
onlyerror(notpacketcompletion)interrupts.ForDMAwithanRXendpoint,theDMAMODEbitinRXCSR
shouldbeclearedto0.
ThecontrollersupportsthefourUSB2.0testmodesdefinedforHigh-speedfunctions.Italsosupportsan
additional“FIFOaccess”testmodethatcanbeusedtotesttheoperationoftheCPUinterface,theDMA
controller(ifconfigured)andtheRAMblock.
ThetestmodesareenteredbywritingtotheTestModeregister(offsetaddress0x40F).Attestmodeis
usuallyrequestedbythehostsendingaSET_FEATURErequesttoEndpoint0.Whenthesoftware
receivestherequest,itshouldwaituntiltheEndpoint0transferhascompleted(whenitreceivesthe
Endpoint0interruptindicatingthestatusphasehascompleted)thenwritetotheTestModeregister.
Note:Thesetestmodeshavenopurposeinnormaloperation.
70UniversalSerialBus(USB)ControllerSPRUGH3–November2008
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