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3.6ResetConsiderations
3.6.1SoftwareResetConsiderations
3.6.2HardwareResetConsiderations
3.6.3USBResetConsiderations
3.7InterruptSupport
3.8EDMAEventSupport
3.9PowerManagement
USBControllerHostandPeripheralModesOperation
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TheUSBcontrollerhastworesetsources:hardwareresetandthesoftreset(RESETbitinCTRLR
register).
WhentheRESETbitinCTRLRisset,alltheUSBcontrollerregistersandDMAoperationsarereset.The
bitisclearedautomatically.
AsoftwareresetontheARMorDSPCPUsdoesnotaffecttheregistervaluesandoperationoftheUSB
controller.
Whenahardwareresetisasserted,alltheregistersaresettotheirdefaultvalues.
Whenoperatinginperipheralmode,aUSBresetreceivedfromthehostcausessomeinternalregistersto
bereset.TheUSBcontrollersetupoperations(forexampleFIFOsizing)inperipheralmodeshouldbe
performedafterreceivingtheUSBreset,andagainoneachsubsequentUSBreset.Therearesome
conditionswheremultipleUSBresetinterruptsmaybereceivedinrapidsuccession.Goodinterrupt
handlingpracticesmustbeobservedtoassurethatthesetupisperformed(again)afterthefinalUSB
resetinterrupt.
SoftwaremustteardownanyTXDMAchanneluseuponreceiptofaUSBreset.SeeSection3.3.2.8.
TheUSBperipheralpresentsasingleinterrupttotheARMinterruptcontroller(AINTC).Forinformationon
themappingofinterrupts,refertothedevice-specificdatamanual.
TheUSBisaninternalbusmasterperipheralandthereforedoesnotutilizeanyEDMAevents.The
registerssupportonlyindividualaccess.BurstingdatatoorfromtheUSBregisterspacethroughEDMAis
notsupported.
TheUSBcontrollercanbeplacedinreducedpowermodestoconservepowerduringperiodsoflow
activity.ThepowermanagementoftheperipheraliscontrolledbytheprocessorPowerandSleep
Controller(PSC).ThePSCactsasamastercontrollerforpowermanagementforalloftheperipheralson
thedevice.FordetailedinformationonpowermanagementproceduresusingthePSC,seethe
TMS320DMxxxDMSoCARMSubsystemReferenceGuide(spru856).
74UniversalSerialBus(USB)ControllerSPRUGH3–November2008
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