Filter
Top Products
3.5.4TEST_PACKET
3.5.5FIFO_ACCESS
USBControllerHostandPeripheralModesOperation
www.ti.com
ToexecutetheTest_Packet,thesoftwareshould:
1.Startasession(ifthecoreisbeingusedinHostmode).
2.Writethestandardtestpacket(shownbelow)totheEndpoint0FIFO.
3.Write0x8totheTestModeregistertoenterTest_Packettestmode.
4.SettheTxPktRdybitintheCSR0register(D1).
The53bytestpackettoloadisasfollows(allbytesinhex).Thetestpacketonlyhastobeloadedonce;
thecontrollerwillkeepre-sendingthetestpacketwithoutanyfurtherinterventionfromthesoftware.
0000000000000000
00AAAAAAAAAAAAAA
AAEEEEEEEEEEEEEE
EEFEFFFFFFFFFFFF
FFFFFFFFFF7FBFDF
EFF7FBFDFC7EBFDF
EFF7FBFD7E
ThisdatasequenceisdefinedinUniversalSerialBusSpecificationRevision2.0,Section7.1.20.The
controllerwilladdtheDATAA0PIDtotheheadofthedatasequenceandtheCRCtotheend.
TheFIFOAccesstestmodeallowstheusertotesttheoperationofCPUInterface,theDMAcontroller(if
configured)andtheRAMblockbyloadingapacketofupto64bytesintotheEndpoint0FIFOandthen
readingitbackoutagain.Endpoint0isusedbecauseitisabi-directionalendpointthatusesthesame
areaofRAMforitsTxandRxFIFOs.
Note:ThecoredoesnotneedtobeconnectedtotheUSBbustorunthistest.Ifitisconnected,
thennosessionshouldbeinprogresswhenthetestisrun.
Thetestprocedureisasfollows:
1.Loadapacketofupto64bytesintotheEndpoint0TxFIFO.
2.SetCSR0.TxPktRdy.
3.Write0x40totheTestmoderegister.
4.UnloadthepacketfromtheEndpointRxFIFO,again.
5.SetCSR0.ServicedRxPktRdy
Writing0x40totheTestmoderegistercausesthefollowingsequenceofevents:
1.TheEndpoint0CPUpointer(whichrecordsthenumberofbytestobetransmitted)iscopiedtothe
Endpoint0USBpointer(whichrecordsthenumberofbytesreceived).
2.TheEndpoint0CPUpointerisreset.
3.CSR0.TxPktRdyiscleared.
4.CSR0.RxPktRdyisset.
5.AnEndpoint0interruptisgenerated(ifenabled).,
TheeffectofthesestepsistomaketheEndpoint0controlleractasifthepacketloadedintotheTxFIFO
hasflushedandthesamepacketreceivedovertheUSB.ThedatathatwasloadedintheTxFIFOcan
nowbereadoutoftheRxFIFO.
UniversalSerialBus(USB)Controller 72SPRUGH3–November2008
SubmitDocumentationFeedback