Filter
Top Products
3.2.4IsochronousTransactions
3.2.4.1HostMode:IsochronousINTransactions
www.ti.com
USBControllerHostandPeripheralModesOperation
AnIsochronousINtransactionisusedtotransferperiodicdatafromtheUSBperipheraltothehost.
ThefollowingoptionalfeaturesareavailableforusewithanRxendpointusedinHostmodetoreceivethis
data:
•Doublepacketbuffering:Whenenabled,uptotwopacketscanbestoredintheFIFOonreception
fromthehost.Thisallowsthatonepacketcanbereceivedwhileanotherisbeingread.Doublepacket
bufferingisenabledbysettingtheDPBbitofRXFIFOSZregister(bit4).
•DMA:IfDMAisenabledfortheendpoint,aDMArequestwillbegeneratedwhenevertheendpointhas
apacketinitsFIFO.ThisfeaturecanbeusedtoallowtheDMAcontrollertounloadpacketsfromthe
FIFOwithoutprocessorintervention.However,thisfeatureisnotparticularlyusefulwithisochronous
endpointsbecausethepacketstransferredareoftennotmaximumpacketsize.
WhenDMAisenabled,endpointinterruptwillnotbegeneratedforcompletionofpacketreception.
Endpointinterruptwillbegeneratedonlyintheerrorconditions.
•AutoRequest:WhentheAutoRequestfeatureisenabled,theREQPKTbitofHOST_RXCSR(bit5)will
beautomaticallysetwhentheRXPKTRDYbitiscleared.
ThisfeatureisapplicableonlywhenDMAisenabled.ToenableAutoRequestfeature,setthe
AUTOREQregisterfortheDMAchannelassociatedfortheendpoint.
3.2.4.1.1Setup
BeforeinitiatinganIsochronousINTransactionsinHostmode:
•ThetargetfunctionaddressneedstobesetintheRXFUNCADDRregisterfortheselectedcontroller
endpoint(RXFUNCADDRregisterisavailableforallendpointsfromEP0toEP4).
•TheHOST_RXTYPEregisterfortheendpointthatistobeusedneedstobeprogrammedasfollows:
–OperatingspeedintheSPEEDbitfield(bits7and6).
–Set01(binaryvalue)inthePROTfieldforisochronoustransfer.
–EndpointNumberofthetargetdeviceinRENDPNfield.Thisistheendpointnumbercontainedin
theRxendpointdescriptorreturnedbythetargetdeviceduringenumeration.
•TheRXMAXPregisterforthecontrollerendpointmustbewrittenwiththemaximumpacketsize(in
bytes)forthetransfer.ThisvalueshouldbethesameasthewMaxPacketSizefieldoftheStandard
EndpointDescriptorforthetargetendpoint.
•TheHOST_RXINTERVALregisterneedstobewrittenwiththerequiredtransactioninterval(usually
onetransactionperframe/microframe).
•TherelevantinterruptenablebitintheINTRRXEregistershouldbeset(ifaninterruptisrequiredfor
thisendpoint).
•ThefollowingbitsofHOST_RXCSRregistershouldbesetasshownbelow:
–SettheDMAENbit(bit13)to1ifaDMArequestisrequiredforthisendpoint.
–CleartheDISNYETit(bit12)to0toallownormalPINGflowcontrol.ThiswillonlyaffectHigh
Speedtransactions.
–AlwayscleartheDMAMODEbit(bit11)to0.
•IfDMAisenabled,AUTOREQregistercanbesetforgeneratingINtokensautomaticallyafterreceiving
thedata.SetthebitfieldRXn_AUTOREQ(wherenistheendpointnumber)withbinaryvalue01or11.
3.2.4.1.2Operation
TheoperationstartswiththesoftwaresettingREQPKTbitofHOST_RXCSR(bit5).Thiscausesthe
controllertosendanINtokentothetarget.
Whenapacketisreceived,aninterruptisgeneratedwhichthesoftwaremayusetounloadthepacket
fromtheFIFOandcleartheRXPKTRDYbitintheHOST_RXCSRregister(bit0)inthesamewayasfora
BulkRxendpoint.Astheinterruptcouldoccuralmostanytimewithinaframe(/microframe),thetimingof
SPRUGH3–November2008UniversalSerialBus(USB)Controller55
SubmitDocumentationFeedback