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4.60ControlStatusRegisterforHostTransmitEndpoint(HOST_TXCSR)
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Registers
TheControlStatusRegisterforHostTransmitEndpoint(HOST_TXCSR)isshowninFigure75and
describedinTable76.
Figure75.ControlStatusRegisterforHostTransmitEndpoint(HOST_TXCSR)
15141312111098
ReservedMODEDMAENFRCDATATOGDMAMODEDATATOGWRENDATATOG
R-0R/W-0R/W-0R/W-0R/W-0W-0R/W-0
76543210
NAK_TIMEOUTCLRDATATOGRXSTALLSETUPPKTFLUSHFIFOERRORFIFONOTEMPTYTXPKTRDY
R/W-0W-0R/W-0R/W-0W-0R/W-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;W=Writeonly;-n=valueafterreset
Table76.ControlStatusRegisterforHostTransmitEndpoint(HOST_TXCSR)FieldDescriptions
BitFieldValueDescription
15-14Reserved0Reserved
13MODE0-1SetthisbittoenabletheendpointdirectionasTx,andclearthisbittoenableitasRx.
Note:ThisbithasanyeffectonlywherethesameendpointFIFOisusedforbothTransmitand
Receivetransactions.
12DMAEN0-1SetthisbittoenabletheDMArequestfortheTxendpoint.
11FRCDATATOG0-1Setthisbittoforcetheendpointdatatoggletoswitchandthedatapackettobeclearedfromthe
FIFO,regardlessofwhetheranACKwasreceived.ThiscanbeusedbyInterruptTxendpointsthat
areusedtocommunicateratefeedbackforIsochronousendpoints.
10DMAMODE0-1WhenusingDMA,clearthisbittoreceiveaninterruptforeachpacket,orsetthisbittoonlyreceive
errorinterrupts.
9DATATOGWREN0-1SetthisbittoenabletheDATATOGbittobewritten.Thisbitisautomaticallyclearedoncethenew
valueiswrittentoDATATOG.
8DATATOG0-1Whenread,thisbitindicatesthecurrentstateoftheTxEPdatatoggle.IfDATATOGWRENishigh,
thisbitcanbewrittenwiththerequiredsettingofthedatatoggle.IfDATATOGWRENislow,any
valuewrittentothisbitisignored.
7NAK_TIMEOUT0-1ThisbitwillbesetwhentheTxendpointishaltedfollowingthereceiptofNAKresponsesforlonger
thanthetimesetastheNAKLIMITbytheTXINTERVALregister.Itshouldbeclearedtoallowthe
endpointtocontinue.
Note:ThisisvalidonlyforBulkendpoints.
6CLRDATATOG0-1Setthisbittoresettheendpointdatatoggleto0.
5RXSTALL0-1ThisbitissetwhenaSTALLhandshakeisreceived.TheFIFOisflushedandtheTXPKTRDYbitis
cleared.Youshouldclearthisbit.
4SETUPPKT0-1SetthisbitatthesametimeasTXPKTRDYisset,tosendaSETUPtokeninsteadofanOUT
tokenforthetransaction.
Note:SettingthisbitalsoclearstheDATATOGbit.
3FLUSHFIFO0-1SetthisbittoflushthenextpackettobetransmittedfromtheendpointTxFIFO.TheFIFOpointer
isresetandtheTXPKTRDYbitiscleared.
Note:FlushFIFOhasnoeffectunlessTXPKTRDYisset.Alsonotethat,iftheFIFOis
double-buffered,FLUSHFIFOmayneedtobesettwicetocompletelycleartheFIFO.
2ERROR0-1TheUSBcontrollersetsthisbitwhen3attemptshavebeenmadetosendapacketandno
handshakepackethasbeenreceived.Youshouldclearthisbit.Aninterruptisgeneratedwhenthe
bitisset.ThisisvalidonlywhentheendpointisoperatinginBulkorInterruptmode.
1FIFONOTEMPTY0-1TheUSBcontrollersetsthisbitwhenthereisatleast1packetintheTxFIFO.
0TXPKTRDY0-1SetthisbitafterloadingadatapacketintotheFIFO.Itisclearedautomaticallywhenadatapacket
hasbeentransmitted.Aninterruptisgenerated(ifenabled)whenthebitiscleared.
SPRUGH3–November2008UniversalSerialBus(USB)Controller123
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