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4.25ReceiveCPPIInterruptEnableClearRegister(RCPPIIENCLRR)
4.26ReceiveBufferCount0Register(RBUFCNT0)
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Registers
TheReceiveCPPIInterruptEnableClearRegister(RCPPIIENCLRR)isshowninFigure40anddescribed
inTable41.
Figure40.ReceiveCPPIInterruptEnableClearRegister(RCPPIIENCLRR)
3116
Reserved
R-0
15430
ReservedCOMP_PENDING_INTR_EN
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table41.ReceiveCPPIInterruptEnableClearRegister(RCPPIIENCLRR)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3-0COMP_PENDING_INTR_EN0-FhReceiveCPPIInterruptEnables
TheseareactivehighinterruptenablescorrespondingtotheReceiveCPPI
CompletionPendingstatusbits.Writinga1toanyofthebitsintheReceiveCPPI
InterruptEnableClearRegisterwillresultinclearingofthecorrespondingbitinthe
ReceiveCPPIInterruptEnableRegister.
TheReceiveBufferCount0Register(RBUFCNT0)isshowninFigure41anddescribedinTable42.
Figure41.ReceiveBufferCount0Register(RBUFCNT0)
3116
Reserved
R-0
150
BUFCNT
R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table42.ReceiveBufferCount0Register(RBUFCNT0)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15-0BUFCNT0-FFFFhReceiveCPPIBufferCount
ThecurrentcountofCPPIbuffersinReceivechannel0queue.Writesaddtocurrentvalue(not
overwrite).TheDMArequiresaminimumof3RXbufferstooperate.
SPRUGH3–November2008UniversalSerialBus(USB)Controller99
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