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3.2.4.2HostMode:IsochronousOutTransactions
USBControllerHostandPeripheralModesOperation
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FIFOunloadrequestswillprobablybeirregular.Ifthedatasinkfortheendpointisgoingtosomeexternal
hardware,itmaybebettertominimizetherequirementforadditionalbufferingbywaitinguntiltheendof
eachframebeforeunloadingtheFIFO.ThiscanbedonebyusingtheSOF_PULSEsignalfromthe
controllertotriggertheunloadingofthedatapacket.TheSOF_PULSEisgeneratedonceper
frame(/microframe).TheinterruptsmaystillbeusedtocleartheRXPKTRDYbitinHOST_RXCSR.
3.2.4.1.3ErrorHandling
IfaCRCorbit-stufferroroccursduringthereceptionofapacket,thepacketwillstillbestoredintheFIFO
buttheDATAERR_NAKTIMEOUTbitofHOST_RXCSR(bit3)issettoindicatethatthedatamaybe
corrupt.
AnIsochronousOUTtransactionmaybeusedtotransferperiodicdatafromthehosttotheUSB
peripheral.
FollowingoptionalfeaturesareavailableforusewithaTxendpointusedinHostmodetotransmitthis
data:
•Doublepacketbuffering:Whenenabled,uptotwopacketscanbestoredintheFIFOawaiting
transmissiontotheperipheraldevice.DoublepacketbufferingisenabledbysettingtheDPBbitof
TXFIFOSZregister(bit4).
•DMA:IfDMAisenabledfortheendpoint,aDMArequestwillbegeneratedwhenevertheendpointis
abletoacceptanotherpacketinitsFIFO.ThisfeaturecanbeusedtoallowtheDMAcontrollertoload
packetsintotheFIFOwithoutprocessorintervention.
However,thisfeatureisnotparticularlyusefulwithisochronousendpointsbecausethepackets
transferredareoftennotmaximumpacketsize.
WhenDMAisenabledandDMAMODEbitinHOST_TXCSRregisterisset,endpointinterruptwillnot
begeneratedforcompletionofpacketreception.Endpointinterruptwillbegeneratedonlyintheerror
conditions.
3.2.4.2.1Setup
BeforeinitiatinganyIsochronousOUTtransactions:
•ThetargetfunctionaddressneedstobesetintheTXFUNCADDRregisterfortheselectedcontroller
endpoint(TXFUNCADDRregisterisavailableforallendpointsfromEP0toEP4).
•TheHOST_TXTYPEregisterfortheendpointthatistobeusedneedstobeprogrammedasfollows:
–OperatingspeedintheSPEEDbitfield(bits7and6).
–Set01(binaryvalue)inthePROTfieldforisochronoustransfer.
–EndpointNumberofthetargetdeviceinTENDPNfield.Thisistheendpointnumbercontainedin
theOUT(Tx)endpointdescriptorreturnedbythetargetdeviceduringenumeration.
•TheTXMAXPregisterforthecontrollerendpointmustbewrittenwiththemaximumpacketsize(in
bytes)forthetransfer.ThisvalueshouldbethesameasthewMaxPacketSizefieldoftheStandard
EndpointDescriptorforthetargetendpoint.
•TheHOST_TXINTERVALregisterneedstobewrittenwiththerequiredtransactioninterval(usually
onetransactionperframe/microframe).
•TherelevantinterruptenablebitintheINTRTXEregistershouldbeset(ifaninterruptisrequiredfor
thisendpoint).
•ThefollowingbitsofHOST_TXCSRregistershouldbesetasshownbelow:
–SettheMODEbit(bit13)to1toensuretheFIFOisenabled(onlynecessaryiftheFIFOisshared
withanRxendpoint).
–SettheDMAENbit(bit12)to1ifaDMArequestisrequiredforthisendpoint.
–TheFRCDATATOGbit(bit12)isignoredforisochronoustransactions.
–SettheDMAMODEbit(bit10)to1whenDMAisenabledandtheendpointinterruptisnotneeded
foreachpackettransmission.
UniversalSerialBus(USB)Controller 56SPRUGH3–November2008
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