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Central Processing Unit: Processor Initialization
10006757-02 PmPPC7448 User’s Manual
3-3
Hardware Implementation Dependent 0 Register
The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specific
features. Most of these bits are cleared on initial power-up of the PmPPC7448. Please refer
to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of
the HIDx registers. The following register map summarizes HID0 for the MPC7448 CPU:
Register 3-1: MPC7448 Hardware Implementation Dependent, HID0
TBE: Time Base Enable—this bit must be set and the TBEN signal must be asserted to enable the
time base and decrementer.
STE: Software Table Search Enable—after a TLB miss, one of the three TLB miss exceptions is
taken so that software can search the page tables for the appropriate PTE.
0 Hardware table search enabled
1 Software table search enabled
HBE: High BATs Enable
0 Additional 4 IBATs (4-7) and 4 DBATs (4-7) disabled
1 Additional 4 IBATs (4-7) and 4 DBATs (4-7) enabled
NAP: Nap Mode Enable
0 Nap mode disabled
1 Nap mode enabled
SLP: Sleep Mode Enable
0 Sleep mode disabled
1 Sleep mode enabled
DPM: Dynamic Power Management Enable
0 Dynamic power management is disabled
1 Functional units enter low-power mode automatically if unit is idle
BHTCLR: Clear Branch History Table
0 The MPC7448 clears this bit one cycle after it is set
1 Setting this bit initializes all entries in BHT
0 4 5 6 7 8 9 10 11 12 13 14 15
reserved TBE RSTEHBENAPSLPDPMR
BHT
CLR
XAE NHR
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ICE DCE
ILO
CK
DLO
CK
ICFI DCFI SPD
XBS
EN
SGE
RBTIC
LRST
K
FOL
D
BHT
NOP
DST
NOP
TI