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System Controller: Device Controller Interface
10006757-02 PmPPC7448 User’s Manual
5-3
• Up to 166 MHz clock frequency
• Support for 256 megabytes to 2 gigabytes
• Up to two gigabytes address space per DRAM bank
• Supports both physical bank (M_CS[3:0]) and virtual bank (M_BA[1:0]) interleaving
The MV64460 has a number of SDRAM registers. Refer to the Marvell web site for available
documentation.
Internal SRAM
The MV64460 integrated SRAM occupies two megabits of space for general purpose mem-
ory. The SRAM is cleared on reset by the monitor to initialize ECC. ECC implementation is
based on 8-bit ECC code per 64-bit of data. ECC support includes:
• Single bit error correction, two bits error detection
• Read-modify-write in case of partial write
• Single bit errors cleanup
• Single and double bit error counters
• Force bad ECC
DEVICE CONTROLLER INTERFACE
The device controller supports up to five banks of devices. Each bank’s supported memory
space can be programmed separately in one megabyte quantities, up to 512 megabytes of
address space, with a total device space of 2.5 gigabytes. Other features include:
• Dedicated 32-bit multiplexed address/data bus (separate from the SDRAM bus)
• Up to 133 MHz bus frequency
• Five chip selects, each with programmable timing
• Use as a high bandwidth interface to user specific logic
• Supports many types of standard memory devices