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Central Processing Unit: Exception Handling
10006757-02 PmPPC7448 User’s Manual
3-7
Instruction Fetch: Synchronous precise exceptions are taken in strict program order.
Instruction Dispatch/Execution:
Imprecise exceptions are delayed until higher priority exceptions are taken.
Post-Instruction Execution:
Maskable asynchronous exceptions are delayed until higher priority exceptions are taken.
Table 3-3: MPC7448 Exception Priorities
Priority: Exception: Notes:
Asynchronous Exceptions (Interrupts)
0 System Reset Power-on reset, assertion of HRESET* and
TRST* (hard reset)
1 Machine Check Any enabled machine check condition
2 System Reset Assertion of SRESET* (soft reset)
3 System Management
Interrupt
Assertion of SMI*
4 External Interrupt Assertion of INT*
5 Performance Monitor Any programmer-specific performance
monitor condition
6 Decrementer Decrementer passes through zero
Instruction Fetch Exceptions
0 Instruction Storage
Interrupt (ISI)
Due to no-execute segment or direct-store
(T=1) segment
1 Instruction Translation
Lookaside Buffer (ITLB)
Miss
Due to miss in ITLB with HID0[STEN]=1
2 ISI Due to effective address that can not be
translated, instruction fetch from guarded
memory, or protection violation
Instruction Dispatch/Execution Exceptions
0 Instruction Address
Breakpoint (IABR)
Highest priority—any instruction address
breakpoint exception condition
1 Program Trap exception, illegal or privileged instruction
2 System call (SC) Execution of system call (sc) instruction
3 Floating-Point Unavailable
(FPA)
Any floating-point unavailable exception
4 AltiVec™ Unavailable Any unavailable AltiVec exception
5 Program (PI) Due to a floating-point enabled exception
6 Alignment Any alignment exception condition
7 Data Storage (DSI) Due to stvx, stvxl, lvx, or lvxl
8Alignment Due to stvx, stvxl, lvx, or lvxl