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Central Processing Unit: Processor Initialization
PmPPC7448 User’s Manual 10006757-02
3-4
XAE: Extended Addressing Enabled
0 Disabled; the 4 MSB bits of the 36-bit physical address are cleared, 32-bit physical
address is used
1 Enabled; the 32-bit effective address is translated to a 36-bit physical address
NHR: Not Hard Reset (software use only)
0 A hard reset occurred if software had previously set this bit
1 A hard reset has not occurred
ICE/DCE: Instruction and Data Cache Enable
0 Instruction and data caches are neither accessed nor updated
1 Instruction and data caches are enabled
I/DLOCK: Instruction and Data Cache Lock bits
0 Normal operation
1 All the ways of the instruction and data caches are locked
ICFI/DCFI: Instruction and Data Cache Flash Invalidate bits
0 Instruction and data caches are not invalidated
1 An invalidate operation is issued that marks the state of each instruction and data
cache block as invalid
SPD: Speculative DCache and ICache Access Disable
0 Bus accesses to nonguarded space from both caches enabled
0 Bus accesses to nonguarded space from both caches disabled
XBSEN: Extended BAT Block Size Enable
0 Disables and clears to zero IBAT[XBL] and DBAT[XBL] bits
1 Enables IBAT[XBL] and DBAT[XBL] bits
SGE: Store Gathering Enable
0Disabled
1Enabled
BTIC: Branch Target Instruction Cache Enable
0 BTIC contents are invalidated and acts as if empty
1 BTIC enables and new entries can be added
LRSTK: Link Register Stack Enable
0 Link register prediction disabled
1Allows bclr and bclrl instructions to predict the branch target address using the link reg-
ister stack
FOLD: Branch Folding Enable
0Disabled
1Enabled