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CPLD: Board Configuration Registers
PmPPC7448 User’s Manual 10006757-02
7-6
Hardware Version Register (HVR)
Register 7-8: Hardware Version Register (HVR) at 0xf820,7000
HVR: Hardware Version number
This is hard coded in the PLD and changes with every major PCB version. Version starts at
00
16
.
PLD Version Register (PVR)
Register 7-9: PLD Version Register (PVR) at 0xf820,8000
PVR: PLD code Version number
This is hard coded in the PLD and changes with every major code change. Version starts at
00
16
.
BOARD CONFIGURATION REGISTERS
Three byte-wide, read-only Board Configuration registers start at location F820,9000
16
.
These registers allow the monitor software to easily determine specific hardware configu-
rations, including Monarch/non-Monarch, DMC status, Boot device, and system clock
speed.
Note: Board Configuration register 2 (0xf820,b000) is not available.
Register 7-10: PmPPC7448 Board Configuration 3 (BCR3) at 0xf820,c000
Reserved: Reserved for future use, default is 0
Mon: Processor PMC Monarch indication
1PPMC is Monarch
0 PPMC is non-Monarch
76543210
HVR
76543210
PVR
76543210
Reserved Mon DMC R