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Serial Input/Output: I2C Interface
PmPPC7448 User’s Manual 10006757-02
8-2
BRGx Tuning Register
A baud tuning mechanism adjusts the generated clock rate to the receive clock rate. When
baud tuning is enabled, the baud tuning mechanism monitors for a start bit (for example
high-to-low transition). Once the start bit is found, the baud tuning machine measures the
bit length by counting up until the next Low-to-High transition. Then the count-up value of
the BRG is loaded into the Count Up Value (CUV) register and a maskable interrupt is gener-
ated signaling the CPU that the bit length value is available. Finally, the CPU reads the value
from the CUV and adjusts the CDV to the requested value.
I
2
C INTERFACE
The MV64460 has full I
2
C interface support, acting as both a master generating read/write
requests and as a slave responding to read/write requests. The I
2
C port consists of two
open drain signals—serial clock (SCL) and serial data/address (SDA).
Note: Marvell documentation refers to this as the Two-Wire Serial Interface (TWSI).
An I
2
C serial configuration ROM is connected to the MV64460’s I
2
C interface, and is dis-
abled by default. Emerson uses the addresses in
Table 8-1 for I
2
C devices.
Table 8-1: I
2
C Device Addresses
I/O CONNECTION
Specific PmPPC7448 configurations provide a standard EIA-232 serial I/O port; P2 is a mini-
USB connector available at the front panel. See
Table 8-2 below. The cable wiring assign-
ments are in
Table 8-3.
Figure 8-1: Front Panel Serial Port Connector (P2)
Device (reference designator): Hex Address:
64460 I
2
C (U33) 0xA4
NVRAM I
2
C (U34) 0xA6
RTC (U36) 0xD0
SO-DIMM I2C (U3) 0xAE
Pin 1