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Central Processing Unit: Exception Processing
10006757-02 PmPPC7448 User’s Manual
3-9
Register 3-3: CPU Machine State Register (MSR)
VEC: AltiVec vector unit available
0 Prevents AltiVec instructions dispatch
1Executes AltiVec instructions
POW: Power Management enable—setting this bit enables the programmable power manage-
ment modes: nap, doze, or sleep. These modes are selected in the HID0 register. This bit
has no effect on dynamic power management.
0 Power management disabled (normal operation mode)
1 Power management enabled (reduced power mode)
ILE: Exception Little-Endian mode—when an exception occurs, ILE is copied into MSR[LE] to
select the endian mode for the context established by the exception.
EE: External Interrupt enable—this bit allows the processor to take an external interrupt, system
management interrupt, or decrementer interrupt.
0 External interrupts and decrementer exception conditions delayed
1 External interrupt or decrementer exception enabled
PR: Privilege level
0 User- and supervisor-level instructions are executed
1 Only user-level instructions are executed
FP: Floating-Point available—this bit is set on initial power-up.
0 Prevents floating-point instructions dispatch (loads, stores, moves)
1 Executes floating-point instructions
ME: Machine Check enable
0 Machine check exceptions disabled
1 Machine check exceptions enabled
FE0/FE1: These bits define the Floating-Point Exception mode:
0 5 6 7 12 13 14 15
reserved VEC reserved
PO
W
RILE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EE PR FP ME FE0 SE BE FE1 RIPIRDRR
PM
M
RI LE
FE0: FE1: FP Exception Mode:
00Disabled
0 1 Imprecise nonrecoverable