CPLD: Interrupt Registers
PmPPC7448 User’s Manual 10006757-02
7-4
Interrupt Enable Register (IER)
Register 7-4: PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000
R: Reserved (default is 000)
SR0EN: PCI0 SERR Enable interrupt routed from PCI0 SERR to MV64460
1 Enabled to generate an interrupt
0 Disabled (default)
PR0EN: PCI0 PERR Enable interrupt routed from PCI0 PERR to MV64460
1 Enabled to generate an interrupt
0 Disabled (default)
Interrupt Pending Register (IPR)
This register allows software to determine which source has caused an interrupt.
Register 7-5: PmPPC7448 Interrupt Pending Register (IPR) at 0xf820,3000
R: Reserved (default is 000)
SERR0: PCI0 SERR Enable
1 SERR has occurred and is enabled (IER SR1EN=1)
0 No SERR (default)
PERR0: PCI0 PERR Enable
1 PERR has occurred and is enabled (IER PR1EN=1)
0No PERR (default)
76543210
Reserved SR0EN PR0EN
76543210
Reserved SERR0 PERR0