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Central Processing Unit: Cache Memory
PmPPC7448 User’s Manual 10006757-02
3-10
SE: Single-Step Trace enable
0 Executes instructions normally
1 Single-step trace exception generated
BE: Branch Trace enable
0 Executes instructions normally
1 Branch type trace exception generated
IP: Exception Prefix
0 Places the exception vector table at the base of RAM (0000,0000
16
)
1 Places the exception vector table at the base of ROM (FFF0,0000
16
)
IR/DR: Instruction and Data address translation enables
0 Address translation disabled
1 Address translation enabled
PMM: Marks a process for the Performance Monitor
0 Process is not marked
1 Process is marked
RI: Recoverable exception enable for system reset and machine check—this feature is enabled
on initial power-up.
0 Exception is not recoverable
1 Exception is recoverable
LE: Little-endian mode enable
0 Big-endian mode (default)
1 Little-endian mode
CACHE MEMORY
L1 Cache
The MPC7448 processor implements two separate 32-kilobyte, level-one (L1) instruction
and data caches that are eight-way, set-associative. The L1 supports a four-state modi-
fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ
pseudo least-recently-used (PLRU) replacement algorithms within each way.
1 0 Imprecise recoverable
11Precise
FE0: FE1: FP Exception Mode: (continued)