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Central Processing Unit: Processor Initialization
10006757-02 PmPPC7448 User’s Manual
3-5
BHT: Branch History Table Enable
0Disabled
1 Allows use of dynamic prediction 2048-entry BHT
NOPDST: No-op the dst, dstt, dstst, and dststt instructions
0 Instructions enabled
1 Instructions are no-oped globally and all previously executed dst streams are cancelled
NOPTI: No-op the dcbt/dcbtst instructions
0 Instructions enabled
1 Instructions are no-oped globally
Hardware Implementation Dependent 1 Register
One of the functions of the Hardware Implementation Dependent 1 (HID1) register is to
display the state of the PLL_CFG[0:5] signals. The following register map summarizes HID1
for the MPC7448 CPU:
Register 3-2: MPC7448 Hardware Implementation Dependent, HID1
EMCP: Machine Check Signal Enable
0Disabled
1 Signal (MCP*) enabled to cause machine check errors or checkstops
EBA: Enable/disable 60x/MPX Bus Address parity checking
0Disabled
1 Allows an address bus parity error to cause a checkstop or machine check exception
EBD: Enable/disable 60x/MPX Bus Data parity checking
0Disabled
1 Allows a data bus parity error to cause a checkstop or machine check exception
BCLK/ECLK: Enable the CLK_OUT output and clock type selection:
012345678910 131415
EMC
P
REBAEBD
BCL
K
R
ECL
K
PAR
DFS
4
DFS
2
reserved PC5 PC0
16 17 18 19 20 21 22 31
PC1 PC2 PC3 PC4
SYN
CBE
ABE
reserved
HRESET*: HID1[ECLK]: HID1[BCLK]: CLK_OUT:
Asserted x x High impedance
Negated 0 0 Zero