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Central Processing Unit: Exception Processing
PmPPC7448 User’s Manual 10006757-02
3-8
EXCEPTION PROCESSING
When an exception occurs, the address saved in Machine Status Save/Restore register 0
(SRR0) helps determine where instruction processing should resume when the exception
handler returns control to the interrupted process. Machine Status Save/Restore register 1
(SRR1) is used to save machine status on exceptions and to restore those values when an rfi
instruction is executed.
When an exception is taken, the MPC7448 controller uses SRR0 and SRR1 to save the con-
tents of the Machine State register (MSR) for the current context and to identify where
instruction execution resumes after the exception is handled.
Machine State Register
The Machine State register (MSR) configures the state of the MPC7448 CPU. On initial
power-up of the PmPPC7448, most of the MSR bits are cleared. Please refer to the MPC7450
RISC Microprocessor Family User’s Manual for more detailed descriptions of the individual bit
fields.
9 Data Storage (DSI) Due to eciwx, ecowx with EAR(E)=0
(DSISR[11])
10 Data Storage (DSI) Due to lwarx/stwcx
11 Data Storage (DSI) Due to BAT/page protection violation
(DSISR[4]) or lwarx/stwcx to BAT entry
12 Data Storage (DSI) Due to any access except cache operations to
SR[T]=1 (DSISR[5]) or T=0->T=1 crossing
13 Data TLB miss on store Due to store miss in DTLB with HID0[STEN]=1
14 Data TLB miss-on-load Due to load miss in DTLB with HID0[STEN]=1
15 Data Storage (DSI) Due to TLB detects page protection violation
(DSISR[4]), lwarx/stwcx to page table entry, or
hardware table search page fault (DSISR[1])
16 Data TLB miss on store Due to HID0[STEN]=1 and the PTE changed bit
not set (C=0) for a store operation
17 Data Storage (DSI) Due to DABR address match (DSISR[9])
18 AltiVec Assist Denormalized data detected as input or output
in the AltiVec vector floating-point unit (VFPU)
while in Java mode (VSCR[NJ]=0)
Post-Instruction Execution Exceptions
19 Trace Lowest priority—due to MSR[SE]=1
(or MSR[BE]=1 for branches)
Priority: Exception: Notes: (continued)