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System Address Map
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Intel
®
82845 MCH for SDR Datasheet 105
4.4 I/O Address Space
The MCH does not support the existence of any other I/O devices beside itself on the system bus.
The MCH generates either hub interface or AGP bus cycles for all processor I/O accesses. The
MCH contains two internal registers in the processor I/O space: Configuration Address
(CONF_ADDR) register and Configuration Data (CONF_DATA) register. These locations are
used to implement the PCI configuration space access mechanism and as described in Chapter 3.
The processor allows 64 KB+3 bytes to be addressed within the I/O space. The MCH propagates
the processor I/O address without any translation on to the destination bus and therefore provides
addressability for 64 KB+3 byte locations. Note that the upper 3 locations can be accessed only
during I/O address wrap-around when signal A16# address signal is asserted. A16# is asserted on
the system bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or
0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
the hub interface unless they fall within the AGP I/O address range as defined by the mechanisms
explained below. The MCH does not post I/O write cycles to IDE.
The MCH never responds to I/O or configuration cycles initiated on AGP or the hub interface.
Hub interface transactions requiring completion are terminated with “master abort” completion
packets on the hub interface. Hub interface write transactions not requiring completion are
dropped. AGP/PCI I/O reads are never acknowledged by the MCH.
4.5 Intel
®
MCH Decode Rules and Cross-Bridge
Address Mapping
The address map described above applies globally to accesses arriving on any of the three
interfaces (i.e., processor system bus, hub interface, or AGP).
4.5.1 Hub Interface Decode Rules
The MCH accepts accesses from the hub interface with the following address ranges:
• All memory read and write accesses to main DRAM (except SMM space).
• All memory write accesses from the hub interface to AGP memory range defined by
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1.
• All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
• Memory writes to VGA range on AGP if enabled.
All memory reads from the hub interface that target >4 GB memory range are terminated with a
master abort completion, and all memory writes (>4 GB) from the hub interface are ignored.