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Intel
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82845 MCH for SDR Datasheet 5
3.6.11
SBUSN1—Secondary Bus Number Register (Device 1) ......................86
3.6.12 SUBUSN1—Subordinate Bus Number Register (Device 1)..................86
3.6.13 SMLT1—Secondary Master Latency Timer Register (Device 1) .........87
3.6.14 IOBASE1—I/O Base Address Register (Device 1) ...............................88
3.6.15 IOLIMIT1—I/O Limit Address Register (Device 1) ................................88
3.6.16 SSTS1—Secondary PCI-PCI Status Register (Device 1) .....................89
3.6.17 MBASE1—Memory Base Address Register (Device 1)........................90
3.6.18 MLIMIT1—Memory Limit Address Register (Device 1).........................90
3.6.19 PMBASE1—Prefetchable Memory Base Address
Register (Device 1)................................................................................91
3.6.20 PMLIMIT1—Prefetchable Memory Limit Address
Register (Device 1)................................................................................91
3.6.21 BCTRL1—PCI-PCI Bridge Control Register (Device 1)........................92
3.6.22 ERRCMD1—Error Command Register (Device 1) ...............................93
3.6.23 DWTC—DRAM Write Thermal Management Control
Register (Device 1)................................................................................94
3.6.24 DRTC—DRAM Read Thermal Management Control
Register (Device 1)................................................................................95
4 System Address Map.........................................................................................................97
4.1 Memory Address Ranges .....................................................................................97
4.1.1 VGA and MDA Memory Space..............................................................99
4.1.2 PAM Memory Spaces..........................................................................100
4.1.3 ISA Hole Memory Space .....................................................................100
4.1.4 TSEG SMM Memory Space................................................................101
4.1.5 IOAPIC Memory Space .......................................................................101
4.1.6 System Bus Interrupt APIC Memory Space ........................................101
4.1.7 High SMM Memory Space...................................................................101
4.1.8 AGP Aperture Space (Device 0 BAR) .................................................102
4.1.9 AGP Memory and Prefetchable Memory.............................................102
4.1.10 Hub Interface Subtractive Decode ......................................................102
4.2 AGP Memory Address Ranges...........................................................................102
4.2.1 AGP DRAM Graphics Aperture...........................................................103
4.3 System Management Mode (SMM) Memory Range...........................................103
4.3.1 SMM Space Definition.........................................................................104
4.3.2 SMM Space Restrictions .....................................................................104
4.4 I/O Address Space..............................................................................................105
4.5 Intel
®
MCH Decode Rules and Cross-Bridge Address Mapping.........................105
4.5.1 Hub Interface Decode Rules ...............................................................105
4.5.2 AGP Interface Decode Rules ..............................................................106
5 Functional Description .....................................................................................................107
5.1 System Bus.........................................................................................................107
5.1.1 Dynamic Bus Inversion........................................................................107
5.1.2 System Bus Interrupt Delivery.............................................................108
5.1.3 Upstream Interrupt Messages.............................................................108
5.2 System Memory Interface...................................................................................109
5.2.1 Single Data Rate (SDR) SDRAM Interface Overview .........................109
5.2.2 Memory Organization and Configuration.............................................109
5.2.2.1 Configuration Mechanism For DIMMs ...............................110
5.2.3 Memory Address Translation and Decoding .......................................111
5.2.4 DRAM Performance Description .........................................................112
5.2.4.1 Data Integrity (ECC)...........................................................112