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Register Description
R
Intel
®
82845 MCH for SDR Datasheet 47
3.5.4 PCISTS—PCI Status Register (Device 0)
Address Offset: 06–07h
Default Value: 0090h
Access: RO, R/WC
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0s on the
hub interface. Since MCH Device 0 is the Host-to-hub interface bridge, many of the bits are not
implemented.
Bit Description
15 Reserved.
14 Signaled System Error (SSE)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH Device 0 generated an SERR message over the hub interface for any enabled Device
0 error condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD
Registers. Device 0 error flags are read/reset from the PCISTS or ERRSTS Registers.
13 Received Master Abort Status (RMAS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH generated a hub interface request that receives a Master Abort completion packet or
Master Abort Special Cycle.
12 Received Target Abort Status (RTAS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH generated a hub interface request that receives a Target Abort completion packet or
Target Abort Special Cycle.
11 Signaled Target Abort Status (STAS)—RO. Not Implemented; Hardwired to 0. The MCH will
not generate a Target Abort hub interface completion packet or special cycle.
10:9 DEVSEL Timing (DEVT)—RO. Hardwired to 00. Hub interface does not comprehend
DEVSEL# protocol.
8 Master Data Parity Error Detected (DPD)—RO. Not Implemented; Hardwired to 0. PERR
signaling and messaging are not implemented by the MCH.
7 Fast Back-to-Back (FB2B)—RO. Hardwired to 1.
6:5 Reserved.
4 Capability List (CLIST)—RO.
1 = Indicates to the configuration software that this device/function implements a list of new
capabilities. A list of new capabilities is accessed via the CAPPTR Register (offset 34h).
CAPPTR contains an offset pointing to the start address within configuration space of this
device where the AGP Capability standard register resides.
3:0 Reserved.