Filter
Top Products
Functional Description
R
Intel
®
82845 MCH for SDR Datasheet 107
5 Functional Description
This chapter describes the system bus that connects the MCH to the processor, the system memory
interface, the AGP interface, the MCH power and thermal management, the MCH clocking, and
the MCH system reset and power sequencing.
5.1 System Bus
The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. Source
synchronous transfers are used for the address and data signals. The address signals are double
pumped and a new address can be generated every other bus clock. At 100 MHz bus frequency,
the address signals run at 200 MT/s for a maximum address queue rate of 50 M addresses/sec. The
data is quad pumped and an entire 64-byte cache line can be transferred in two bus clocks. At
100 MHz bus frequency, the data signals run at 400 MT/s for a maximum bandwidth of 3.2 GB/s.
The MCH supports a 12 deep IOQ.
The MCH supports two outstanding deferred transactions on the system bus. The two transactions
must target different I/O interfaces as only one deferred transaction can be outstanding to any
single I/O interface at a time.
5.1.1 Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from the
system bus. DBI limits the number of data signals that are driven to a low voltage on each quad
pumped data phase. This decreases the power consumption of the MCH. DBI[3:0]# indicates if the
corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
DBI[3:0]# Data Bits
DBI0# HD[15:0]#
DBI1# HD[31:16]#
DBI2# HD[47:32]#
DBI3# HD[63:48]#
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more than 8 of
the 16 signals would normally be driven low on the bus, the corresponding DBI# signal will be
asserted and the data will be inverted prior to being driven on the bus. When the processor or the
MCH receives data, it monitors DBI[3:0]# to determine if the corresponding data segment should
be inverted.