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Register Description
R
Intel
®
82845 MCH for SDR Datasheet 37
3.4.1 DRAMWIDTH—DRAM Width Register
Address Offset: 2Ch
Default Value: 00h
Access: R/W
Size: 8 bits
This register determines the width of SDRAM devices populated in each row of memory.
Bit Descriptions
7:6 Reserved.
5 Row 5 Width. Width of devices in Row 5
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
4 Row 4 Width. Width of devices in Row 4
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
3 Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
2 Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
1 Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
0 Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify
exactly which row width field affects which clock signal.
Row Parameters SDR Clocks Affected
0 SCK[0], SCK[2]
1 SCK[1], SCK[3]
2 SCK[4], SCK[6]
3 SCK[5], SCK[7]
4 SCK[8], SCK[10]
5 SCK[9], SCK[11]