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Register Description
R
86 Intel
®
82845 MCH for SDR Datasheet
3.6.11 SBUSN1—Secondary Bus Number Register (Device 1)
Offset: 19h
Default: 00h
Access: R/W
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI
bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to AGP.
Bit Descriptions
7:0 Bus Number. Programmable. Default = 00h.
3.6.12 SUBUSN1—Subordinate Bus Number Register (Device 1)
Offset: 1Ah
Default: 00h
Access: R/W
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to AGP.
Bit Descriptions
7:0 Bus Number. Programmable. Default = 0.