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Register Description
R
Intel
®
82845 MCH for SDR Datasheet 83
3.6.4 PCISTS1—PCI-PCI Status Register (Device 1)
Address Offset: 06–07h
Default Value: 00A0h
Access: RO, R/WC
Size: 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
primary side of the “virtual” PCI-PCI bridge embedded n the MCH. Since this device does not
physically reside on PCI_A, it reports the optimum operating conditions so that it does not restrict
the capability of PCI_A.
Bit Descriptions
15 Detected Parity Error (DPE1)—RO. Not Implemented; Hardwired to 0.
14 Signaled System Error (SSE1)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH device 1 generated an SERR message over the hub interface for any enabled Device
1 error condition. Device 1 error conditions are enabled in the ERRCMD, PCICMD1 and
BCTRL1 registers. Device 1 error flags are read/reset from the ERRSTS and SSTS1
register.
13 Received Master Abort Status (RMAS1)—RO. Not Implemented; Hardwired to 0.
12 Received Target Abort Status (RTAS1)—RO. Not Implemented; Hardwired to 0.
11 Signaled Target Abort Status (STAS1)—RO. Not Implemented; Hardwired to 0.
10:9 DEVSEL# Timing (DEVT1)—RO. Hardwired to 00b. Indicate that the device 1 uses the fastest
possible decode.
8 Data Parity Detected (DPD1). Not Implemented; Hardwired to 0.
7 Fast Back-to-Back (FB2B1)—RO. Hardwired to 1. The AGP port always supports fast back to
back transactions.
6 Reserved.
5 66 MHz Capability (CAP66)—RO. Hardwired to 1. Indicates that the AGP port is 66 MHz
capable.
4:0 Reserved.