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Register Description
R
Intel
®
82845 MCH for SDR Datasheet 85
3.6.8 MLT1—Master Latency Timer Register (Device 1)
Address Offset: 0Dh
Default Value: 00h
Access: R/W
Size: 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as
a read/write to prevent standard PCI-PCI bridge configuration software from getting “confused”.
Bit Description
7:3 Not applicable but supports read/write operations. (Reads return previously written data.)
2:0 Reserved.
3.6.9 HDR1—Header Type Register (Device 1)
Offset: 0Eh
Default: 01h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space.
Bit Descriptions
7:0 This read only field always returns 01h when read. Writes have no effect.
3.6.10 PBUSN1—Primary Bus Number Register (Device 1)
Offset: 18h
Default: 00h
Access: RO
Size: 8 bits
This register identifies that “virtual” PCI-PCI Bridge is connected to bus #0.
Bit Descriptions
7:0 Bus Number. Hardwired to 0.