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Register Description
R
36 Intel
®
82845 MCH for SDR Datasheet
3.3.2 CONF_DATA—Configuration Data Register
I/O Address: 0CFCh
Default Value: 00000000h
Access: R/W
Size: 32 bits
CONF_DATA is a 32 bit read/write window into configuration space. The portion of
configuration space that is referenced by CONF_DATA is determined by the contents of
CONF_ADDR.
Bit Descriptions
31:0 Configuration Data Window (CDW). If bit 31 of the CONF_ADDR register is 1, any I/O access
to the CONF_DATA register will be mapped to configuration space using the contents of
CONF_ADDR.
3.4 Memory-Mapped Register Space
All system memory control functions have been consolidated into a new memory-mapped address
region within Device 0, Function 0. This space will be accessed using a new Base Address register
(BAR) located at Device 0, Function 0 (address offset 14h). By default this BAR is invisible
(i.e., read-only as 0s).
Note: All accesses to these memory-mapped registers must be made as a single DWord (4 bytes) or less.
Access must be aligned on a natural boundary.
The high-level address map for the memory-mapped registers is shown in Table 7.
Table 7. Memory-mapped Register Address Map
Memory Address Offset Register Group
020h–02Bh Reserved
2Ch DRAM Width Register
02Dh–02Fh Reserved
030h–034h Strength Registers
040h–0DFh Reserved
140h–1DFh Reserved