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Functional Description
R
114 Intel
®
82845 MCH for SDR Datasheet
5.3.2 AGP Transaction Ordering
The MCH observes transaction ordering rules as defined by the AGP Interface Specification,
Revision 2.0.
5.3.3 AGP Signal Levels
The 4x data transfers use 1.5 V signaling levels as described by the AGP Interface Specification,
Revision 2.0. The MCH supports 1x/2x data transfers using 1.5 V signaling levels.
5.3.4 4x AGP Protocol
In addition to the 1x and 2x AGP protocol, the MCH supports 4x AGP read and write data
transfers and 4x sideband address generation. The 4x operation is compliant with the AGP
Interface Specification, Revision 2.0.
The MCH indicates that it supports 4x data transfers via bit 2 of the AGPSTAT.RATE field.
When bit 2 of the AGPCMD.DRATE field is set to 1 during system initialization, the MCH
performs AGP read/write data transactions using 4x protocol. This bit is not dynamic. Once this
bit is set during initialization, the data transfer rate must not be changed.
The 4x data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4x
data transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred on
every 66 MHz clock edge. The minimum throttleable block size remains four 66 MHz clocks
(64 bytes of data are transferred per block). Three additional signal pins are required to implement
the 4x data transfer protocol. These signal pins are complimentary data transfer strobes for the AD
bus (2) and the SBA bus (1).
5.3.5 Fast Writes
The MCH supports 2x and 4x Fast Writes from the MCH to the graphics controller on AGP. Fast
Write operation is compliant with Fast Writes as currently described in the AGP Interface
Specification, Revision 2.0. To use the Fast Write protocol, both AGPCTRL.FWCE and
AGPCMD.FWPE must be set to 1.
AGPCTRL.FWCE is set to 0 by default. When this bit is set to 1, the MCH indicates that it
supports Fast Writes through AGPSTAT.FW. When both AGPCMD.FWEN and
AGPCTRL.FWCE are set to 1, the MCH uses Fast Write protocol to transfer memory write data to
the AGP master.
Memory writes originating from the processor or from the hub interface use the Fast Write
protocol when it is both capability enabled and enabled. The data rate used to perform the Fast
Writes is dependent on the bits set in the AGPCMD.DRATE field (bits [2:0]). If bit 2 of the
AGPCMD.DRATE field is 1, the data transfers occur using 4x strobing. If bit 1 of
AGPCMD.DRATE field is 1, the data transfers occur using 2x strobing. If bit 0 of
AGPCMD.DRATE field is 1, Fast Writes are disabled and data transfers occur using standard PCI
protocol. Note that only one of the three DRATE bits can be set by initialization software
(Table 16).