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Thermal/Mechanical Specifications and Design Guidelines 57
Thermal Specifications
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
6.2.2.3 Immediate Transition to combined TM1 and TM2
As mentioned above, when the TCC is activated the processor will sequentially step
down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature. If
the temperature continues to increase and exceeds the TCC activation temperature by
approximately 5
o
C before the lowest ratio/VID combination has been reached, then
the processor will immediately transition to the combined TM1/TM2 condition. The
processor will remain in this state until the temperature has dropped below the TCC
activation point. Once below the TCC activation temperature, TM1 will be discontinued
and TM2 will be exited by stepping up to the appropriate ratio/VID state.
6.2.2.4 Critical Temperature Flag
If TM2 is unable to reduce the processor temperature, then TM1 will be also be
activated. TM1 and TM2 will then work together to reduce power dissipation and
temperature. It is expected that only a catastrophic thermal solution failure would
create a situation where both TM1 and TM2 are active.
If TM1 and TM2 have both been active for greater than 20ms and the processor
temperature has not dropped below the TCC activation point, then the Critical
Temperature Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator
of a catastrophic thermal solution failure and that the processor cannot reduce its
temperature. Unless immediate action is taken to resolve the failure, the processor will
probably reach the Thermtrip temperature (see Section 6.2.3 Thermtrip Signal) within
a short time. In order to prevent possible permanent silicon damage, Intel
recommends removing power from the processor within ½ second of the Critical
Temperature Flag being set.
6.2.2.5 PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled
(note it must be enabled for the processor to be operating within specification), the
TCC will be active when PROCHOT# is asserted.
The processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#.
Although the PROCHOT# signal is an output by default, it may be configured as bi-
directional. When configured in bi-directional mode, it is either an output indicating the
processor has exceeded its TCC activation temperature or it can be driven from an
external source (such as, a voltage regulator) to activate the TCC. The ability to
activate the TCC via PROCHOT# can provide a means for thermal protection of system
components.
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that one or more cores has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC for all cores. TCC activation when
PROCHOT# is asserted by the system will result in the processor immediately